1. Field of the Invention
The present invention relates to a one-chip microcomputer and more particularly to a one-chip microcomputer which can access an external memory.
2. Prior Art
In general, a one-chip microcomputer has a ROM within itself (hereinafter, referred to as an internal ROM) and operates according to a program contained in the ROM. The one-chip microcomputer may also have a ROM connected externally (hereinafter, referred to as an external ROM) and operate according to the instructions read out of the external ROM via the data input terminals of the one-chip microcomputer.
An example of a one-chip microcomputer of this type is disclosed in Japanese Unexamined Patent Publication No. 62-156737. The system disclosed in the patent publication is able to execute either a program stored in the internal ROM or a program stored in the external ROM. Then, it has a switching circuit which switches the operation between the internal ROM and the external ROM as well as an instruction register which, upon receiving an output from the switching circuit, holds an instruction necessary for operation of the one-chip microcomputer.
The switching circuit comprises the switching gates for selecting internal ROM data or external ROM data. Within the one-chip microcomputer are generated internal signals, which are followed by the internal ROM operation and the external ROM operation. In summary, pursuant to the internal signals, the internal ROM or the external ROM is selected, the control signal to control the external ROM operation is generated, and the timing signal to allow latching of an instruction in the instruction register is generated.
FIG. 3 is a timing chart to depict memory access of a one-chip microcomputer with the switching circuit to select one of the internal ROM and the external ROM. In FIG. 3, OSC denotes the output signal of an oscillator, 1/2OSC denotes a signal with half of the output signal frequency, ALE denotes an Address Latch Enable (ALE) signal, PSEN (low-active signal) denotes a strobe signal for the read operation. The top half (a) of the figure is the timing chart of the internal ROM, and the bottom half (b) is that of the external ROM. The operation shown in FIG. 3(a) and that shown in FIG. 3(b) are basically the same except that the ALE signal, PSEN signal, and address signal in FIG. 3(b) lag behind those in FIG. 3(a). This delay is caused by factors such as capacitance of the terminals and circuits lying in the vicinity thereof.
As shown in FIG. 3(b), when the external ROM is selected, the one-chip microcomputer specifies an address for the external ROM on the falling edge of the Address Latch Enable (ALE) signal. And, when the PSEN signal falls, an instruction is read from the data bus terminal of the external ROM. When the ROM data fetch signal rises, the instruction is fetched into a CPU.
As described above, the switching circuit in a conventional one-chip microcomputer simply selects the internal ROM or external ROM based on the internal signal. There is no measure to permit access of the external memory in an access time similar to that of the internal memory.
Therefore, when the internal ROM is selected, there is no problem with instruction fetching because of no delay in fetching an instruction into the instruction register. On the contrary, when the external ROM is selected, there may be a problem with instruction fetching because of a delay in fetching an instruction into the instruction register. In short, the timing in which an instruction is fetched from the external ROM lags behind the timing in which an instruction is fetched from the internal ROM. As a result, there is not enough time for instruction fetching of the external ROM in comparison with the internal ROM.
Such a condition requires an external ROM capable of operating faster to compensate for the delay in instruction fetching, thereby leading to increased cost.